FIG. 1A is a schematic functional block diagram illustrating a conventional phase locked loop. The phase locked loop (PLL) 10 includes a phase/frequency detector (PFD) 101, a charge pump (CP) 103, a low pass filter (LPF) 105 and a voltage control oscillator (VCO) 107. The phase locked loop 10 is optionally comprised of a frequency divider 109. The operating principle of the phase locked loop 10 will be illustrated as follows. Firstly, a divided signal Vdiv from the frequency divider 109 and an input signal Vin are received by the phase/frequency detector 101. Then, a phase difference between the divided signal Vdiv and the input signal Vin is detected. According to the phase difference, the frequency of an output signal Vout from the voltage control oscillator 107 is adjusted. The frequency of the output signal Vout is divided by the frequency divider 109, and the divided signal Vdiv is issued to the phase detector 101. Ideally, the frequency of the divided signal Vdiv is identical to that of the input signal Vin.
FIG. 1B is a schematic diagram illustrating the interconnection among the phase/frequency detector, the charge pump, and the low pass filter. After the phase/frequency detector 101 receives the input signal Vin and the divided signal Vdiv, the phase/frequency detector 101 outputs comparing signals (Vup, Vdown). The comparing signals (Vup, Vdown) are used for respectively controlling the switching states of the semiconductor devices (P1, N1) in the charge pump 103. Consequently, the low pass filter 105 is charged or discharged in response to the switching states of the semiconductor devices (P1, N1).
Charging/discharging the low pass filter 105 results in changes of the voltage level VCP at the current output node SCP, and further affects the frequency of the output signal Vout generated and outputted from the voltage control oscillator 107.
The operations of the phase/frequency detector 101, charge pump 103, low pass filter 105, and voltage control oscillator 107 will be further discussed below.
In a case that the frequency of the input signal Vin is greater than frequency of the divided signal Vdiv, the charge pump 103 charges the low pass filter 105 according to the first comparing signal Vup. After being charged, the voltage level VCP at the current output node SCP is increased, and so are the frequencies of the output signal Vout and the divided signal Vdiv.
Therefore, the increase of the voltage level VCP at the current output node SCP indirectly causes the increase of the frequency of the divided signal Vdiv. In spite the frequency of the divided signal Vdiv less than the frequency of the input signal Vin at the first, the frequencies of the output signal Vout and the divided signal, Vdiv become higher as the low pass filter 105 is charged. As a result, by increasing the voltage level VCP at the current output node SCP, the frequency of the divided signal Vdiv increases so as to approach the frequency of the input signal Vin.
In a case that the frequency of the input signal Vin is less than that of the divided signal Vdiv, the charge pump 103 discharges the low pass filter 105 according to the second comparing signal Vdown generated from the phase/frequency detector. After discharging, the voltage level VCP at the current output node SCP is decreased, and so are the frequencies of the output signal Vout and the divided signal Vdiv.
Therefore, the decrease of the voltage level VCP at the current output node SCP indirectly causes the decrease of the frequency of the divided signal Vdiv. In spite the frequency of the divided signal Vdiv is greater than the frequency of the input signal Vin at the first, the frequencies of the output signal Vout and the divided signal Vdiv become less as the low pass filter 105 is discharged. As a result, by decreasing the voltage level VCP at the current output node SCP, the frequency of the divided signal Vdiv decreases so as to approach the frequency of the input signal Vin.
In brief, since the voltage level VCP at the current output node SCP correlates to the frequencies of the output signal Vout and divided signal Vdiv, the control of the voltage level VCP at the current output node SCP facilitates the stabilization of the phase locked loop 10. It is shown that the control of the voltage level VCP is an important issue.
In details, with reference to FIG. 1B, an inverted first comparing signal Vup′ is generated by inverting the first comparing signal Vup. by an inverter 102a and received by the charge pump 103.
According to the inverted first comparing signal Vup′, the switching state of the first p-channel metal-oxide-semiconductor (PMOS) P1 is determined. In a case that the logic state of the first comparing signal Vup is logic “1”, then the logic state of the inverted first comparing signal Vup′ is logic “0”, and the first PMOS P1 is turned on. In such a case, the low pass filter 105 is charged by the charge pump 103 and the voltage level VCP at the current output node SCP is increased accordingly.
On the other hand, the second comparing signal Vdown is propagated via a transmission gate 102b. The propagated second comparing signal VdownΔ is received by the charge pump 103.
With the propagated second comparing signal VdownΔ, the switching state of the first n-channel metal-oxide-semiconductor (NMOS) N1 is determined. In a case that the logic state of the propagated second comparing signal VdownΔ is logic “1”, the first NMOS N1 is turned on. In such a case, the low pass filter 105 is discharged by the charge pump 103 and the voltage level VCP at the current output node SCP is decreased accordingly.
From the above discussions, in a case that logic states of the first and second comparing signals Vup, Vdown are logic “0”, the first PMOS P1 and the first NMOS N1 are both turned off. In such a case, the voltage level VCP at the current output node SCP becomes floating.
If the voltage control oscillator 107 receives the floating voltage level VCP at the current output node SCP, jitters are easily generated as noises might be occurred. Therefore, how to stabilize the voltage level VCP when both the comparing signals Vup, Vdown are high impedance is an important issue.
Ideally, the influences of the charging operation of the first and second PMOS, and the discharging operation of the first and second NMOS on the low pass filter 105 can be balanced. However, these two types of transistors are not completely symmetrical to each other in practice, and the intensities of the charging current and the discharging current are hard to completely equal to each other.